SdrNav40

Please note the text and sub-pages below is for reference only as we officially ceased operations now.

Building on SdrNav20, after a small glitch with SdrNav21 and its MAX1193, we went back to the well known MAX195xx ADC and built an even more powerful version with 4 parallel channels, very well synchronised.


The main characteristics are:
- Wide input voltage range of 8-28V with polarity protection
- Expansion header with 18 signals
- Xilinx Spartan6 FPGA (6SLX4TQG144)
- Cypress FX2LP
- IDT ICS512 clock upscaler with internal/external input
- IDT ICS551 clock distribution
- 4x MAX21xx + MAX195xx receive RF chains


ĉ
Michele Bavaro,
12 Jun 2016, 02:06